Dr. Eric Durant: EE-393 VLSI Design

Textbook

Kang, Sung-Mo and Leblebici, Yusuf, CMOS Digital Integrated Circuits: Analysis and Design, 3 ed, McGraw-Hill, 2003.

Additional Readings

Mouli, Chandra and Carriker, Wayne. Future Fab: How software is helping Intel go nano—and beyond. IEEE Spectrum, Vol. 44, no. 3 (NA), March 2007, pp. 38-43.
Goodnick, Stephen M. Future Nanoelectronic Technologies: Overcoming Semiconductor Limits. The Bridge: The Magazine of Eta Kappa Nu, Spring 2006, pp. 4-5 (abridged print version).
Cavin, III, Ralph K. and Zhirnov, Victor. Semiconductor Technologies for 2025: Needs, Challenges, and Opportunities. The Bridge: The Magazine of Eta Kappa Nu, Autumn 2005, pp. 4-5 (abridged print version).
University of Virginia Virtual Lab Animations, especially…
- Silicon crystals, doping, and the MOSFET
- IC construction, oxide growth, etching, polysilicon growth, masking, etc.
Michels, Spencer. Intel Works on Faster Computer Chip Technology. Online NewsHour, Originally Aired 7 May 2007.
Bohr, Mark T., Robert S. Chau, Tahir Ghani, and Kaizad Mistry. The High-k Solution. IEEE Spectrum Online, October 2007.
Boyd, S. et al. Digital Circuit Optimization via Geometric Programming. Operations Research, November 2005.

Lab assignments

Lab reports will be submitted by email to durant@msoe.edu. They must meet the specifications given in the assignment. Generally this means submitting a well organized collection of key calculations, schematics, layouts, and PSpice waveforms with a cover page. A brief caption should be included explaining each figure. A detailed narrative is not required. The report must be contained in a single Word file or PDF. If additional files need to be submitted, combine them with your report in a single Zip archive.

(Week 1-2, due week 3 by lab) Lab 1: PSpice: CMOS transistors using T15D process from MOSIS: NMOS/PMOS curves; CMOS inverter
(Week 3-4, due week 5 by lab) Lab 2
(Week 5-6, due Friday of week 7) Lab 3
(Week 7-8, due Friday of week 8) Lab 4, BJT_NPN.txt
(Week 9-10, due Friday of week 10) Lab 5, PSpice Schmitt Trigger Schematic

Software

Starting with lab 1, you will need a version of PSpice with schematic support. The recommended version is 9.1, which is what is on the MSOE images. You can download it from [link no longer available]. If you have a newer version from another class, that will work as well. (Note that the complete OrCAD 10.5 demo CD is also available, but OrCAD has removed schematics support from this version.)

Software needed for later labs (not currently posted on this website): Microwind 2.7, Dsch 2.7

References from Dr. Durant

Using PARAM to easily change clock frequency (PDF)

References from Dr. Acharya and Dr. Durant

References from Dr. Acharya

Updated (4/24/2007) Microwind T15D rule file with 3.3/5 V and level-3 model parameters (copy and paste to editor to ensure DOS text format; Microwind cannot handle UNIX text format correctly)
Solution worksheet for problems 5.1 and 5.2 (Excel)
Problem set for quiz and 2nd midterm (Word)
MOS Capacitances Formulae (PDF)
MOS Capacitors (Excel)
VLSI Layout Using Microwind2 (PowerPoint) (updated Wednesday 4/4 with 3 new slides including naming nodes and viewing SPICE netlist)
OLD Microwind T15D rule file (*copy and paste to editor to ensure DOS text format; Microwind cannot handle UNIX text format correctly*)
Week 2 homework, preparing for 3/28 midterm (Word)
CMOS inverter design example problems (Word)
Physics Review Practice Problems (Word)
VLSI Process Model (Word)
MOSFET diagram and dimensions (Excel)
PSpice Introduction (PowerPoint)
Lecture 1 review (PowerPoint)
Lecture 1B review (PowerPoint)

Schedule

	Monday	Tuesday	Wednesday	Thursday	Friday
Section 2			Lab CC-46 12:00-2:50 P.M.

Note: Everyone will attend the section 1 lecture, which meets Mondays and Wednesdays from 5:30 to 6:45 PM.

Course policies

Grading algorithm

Your 5 lab grades will be forwarded to the lecture instructor for calculation of your course grade.