Dr. Durant: CE-1910 Digital Logic II: Sequential Systems

Main course website (not currently active)

The main course website includes textbook information, weekly lab objectives, course-specific policies, and daily learning objectives. A few additional items are posted here…

• Final exam from spring, 2009
• Clock dividers
  • 2011: The clock divider in the book works well with the UP2 board and the current version of Quartus.
  • 2009: Clock divider from Prof. Barnekow, works well on the UP2 board in some older versions of Quartus.
• VHDL review sheet (week 7)
• VHDL integer conversions

Additional readings - 2009

• Gallagher, Kathleen. Managers hope fund cashes in on new computer chips. Milwaukee Journal-Sentinel, 25 February 2008.
• Santo, Brian and Sally Adee. Multicore Made Simple: Intel’s Larrabee is a chip every designer already knows how to program. IEEE Spectrum, January 2009.

Lab

Weekly lab details will be available on the main course website. All prelab assignments and in-lab activities will be conducted individually, but you are free to consult with other students and the professor. All lab assignments will be weighted equally by weeks (2-week labs count twice as much as 1-week labs) and will be evaluated using a provided check-out sheet.

Lab Check-out Sheets

• …will be posted here when available

General course policies

Quizzes

Quizzes will be given during the first 15 minutes of most lab periods. The lowest quiz grade will be dropped. No make-up quizzes will be given.

Final exam

The final exam will be given per the schedule that is published by the Registrar’s Office in approximately week 6. It may cover any of the learning objectives from the course, which are posted on the main course website. The exam will last 2 hours. No notes, books, calculators, etc. may be used on the final.

Optional homework

Grading algorithm