Dr. Durant: CE-1901 Digital Logic I

Main course website [moved since I last taught this course]

The main course website includes textbook information, weekly lab objectives, course-specific policies, and daily learning objectives.

Lab

Weekly lab details will be available on the main course website. All prelab assignments will be conducted individually. Some in-lab activities will be conducted in pairs. All lab assignments will be weighted equally by weeks (2-week labs count twice as much as 1-week labs) and will be evaluated using a checklist provided by the instructor.

Lab Check-out Sheets

Old Additional Practice Problems

Quartus Checklist

Especially when working with multi-entity projects and the simulator, Quartus sometimes gives unexpected errors. This checklist will eliminate virtually all of these errors, although often it is not necessary to follow all of these items.

  1. Use lowercase (or uppercase) exclusively for all named items (ports, signals, structural instances, etc.)
  2. Use that same case for the project and filename.
  3. Don't have spaces or punctuation in the project name
  4. Don't have spaces or punctuation in the project directory name itself, but parent directories can have spaces
  5. One directory per project
  6. Only necessary files in project (from Project Navigator [View | Utility Windows | Project Navigator if needed], click Files tab. Right-click and remove any unnecessary files, especially BDF or VHD files).
  7. Have the project name match the top-level entity name
  8. Have the directory name match the project name
  9. Have the design file with the top-level entity have a file name base that is the same as the entity name
  10. Have the top-level entity name set correctly to the entity to be simulated (to fix, select Project | Set as Top-Level entity while viewing the entity to simulate)
  11. After using certain reserved words for port names the design will appear to synthesize correctly but will fail during simulation (common examples: "i", "input", "output")
  12. If part or all of the crosshatching (unknown values) remains after simulating, you may have mismatched or illegal input/output names in your entity and VWF. Ctrl-K to ensure your latest node names are available to the waveform editor. Correct input/output node names in VWF if you recognize the problem, otherwise delete and re-add them.
  13. Choosing an unlicensed chip type (one not available free for university use) will cause various problems including simulations silently failing in some cases. If you select a chip, be sure it is a licensed one. See the first CE1901 Quartus tutorial regarding which chip you should select for your DE0-Nano board.
  14. If nothing above solves the problem and your project synthesizes correctly (no errors after Ctrl-K) but generates non-correctable errors during simulation (usually a status of "Errors during simulation" with no further information), re-installing just the simulator may help. Run ModelSimSetup-<version>. If you get a warning that this will create "instance 2" or similar of the installer, it seems to be necessary to uninstall and re-install all of Quartus. If you simply receive a warning that the simulator is already installed (or no warning at all), this should work.
  15. Uninstall/reinstall Quartus. Avoid spaces in install directory.

Readings

2016

2015

2014

2013

Examples

Quizzes

Quizzes will be given during the first 15 minutes of most lab periods. The lowest quiz grade will be dropped. No make-up quizzes will be given.

Quiz solutions

Final exam

The final exam will be given per the schedule that is published by the Registrar's Office in approximately week 6. It may cover any of the learning objectives from the course, which are posted on the main course website. The exam will last 2 hours. No notes, books, calculators, etc. may be used on the final.

General course policies

Grading algorithm

Labs 33⅓%
Quizzes 33⅓%
Final Exam 33⅓%